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ECET 230

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ECET 230  Week 1 Homework NEW 1. Develop the Boolean equation for the circuit shown below 2. Determine the output Y in Problem 1 for the input values shown below 3. Redraw the circuit in Problem 1 using only 2-input NAND gates 4.Develop the Boolean equation for the circuit shown bel..
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ECET 230  Week 2 Homework NEW 1. When a HIGH is on the output of the decoding circuit below, what is the binary code appearing on the inputs? 2. Write the Boolean equations for each of the following codes if an active-LOW decoder output is required: 3. Write the VHDL text file for a 3-..
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ECET 230 Week 1 iLab Introduction to Quartus II, VHDL, and the FPGA Board NEW Objectives: 1.Learn How to write basic logic circuits using VHDL. 2.Using Quartus II compile and simulate the text file and then analyze the simulation for proper operation. 3.Learn how to assign pins and then ..
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ECET 230 Week 2 iLab Decoders and Multiplexers NEW Objectives: Discover the operation of 7-segment displays, BCD-to-7-semgment decoders, multiplexers and demultiplexers.  Demonstrate the simulation of a discrete DEMUX and decode operation with discrete components.  Construct a disc..
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ECET 230 Week 3 Homework NEW 1.Determine the decimal value of each of the following unsigned binary numbers: 2.Determine the decimal value of each of the following signed binary number displayed in the 2’s complement form: 3. Determine the outputs (Cout, Sout) of a full-..
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ECET 230 Week 3 Homework NEW 1.Determine the decimal value of each of the following unsigned binary numbers: 2.Determine the decimal value of each of the following signed binary number displayed in the 2’s complement form: 3. Determine the outputs (Cout, Sout) of a full-..
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ECET 230 Week 3 iLab Flip-Flops in VHDL NEW Objectives:  Simulate an edge-triggered D flip-flop.  Test a 74LS74 D flip-flop and compare against predictions.  Describe and simulate edge-triggered D and J-K flip-flops with VHDL.  Test a 74LS112 J-K flip-flop and compare aga..
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ECET 230 Week 4 Homework NEW 1. Sketch the Q output for the waveforms shown below applied to an active-LOW S-R latch. Assume that Q starts LOW. 2. Sketch the Q output for the waveforms shown. Assume that Q starts LOW. 3. Sketch the Q output for the circuit shown below. Assume that Q st..
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ECET 230 Week 4 iLab Introduction to Flip-Flops NEW Objectives:  Simulate an edge-triggered D flip-flop.  Test a 74LS74 D flip-flop and compare against predictions.  Describe and simulate edge-triggered D and J-K flip-flops with VHDL.  Test a 74LS112 J-K flip-flop and com..
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ECET 230 Week 5 Homework NEW 1.Using Quartus II, or an equivalent VHDL entry program, develop the text file and simulation for the circuit below. Attach the .vhd and simulation files. 2.What is the output frequency of Q1 in the circuit shown below? 3.A synchronous binary counter is used to ..
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ECET 230 Week 5 iLab Design of Synchronous Counters NEW Objectives: 1.To understand the how to design sequential counters using a VHDL logic design file. 2.To design a basic synchronous up binary counter using the VHDL Integer type. 3.To be able to use IF…THEN…ELSE statements in the desi..
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ECET 230 Week 6 Homework NEW 1.The group of bits 10110101 is serially shifted (right-most bit first) into an 8-bit shift register with an initial state of 11100100. After two clock pulses, the register contains: (a) 01011110 (b) 10110101 (c) 01111001 (d) 00101101 2. With a 100 kHz clock fre..
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ECET 230 Week 6 iLab Design of a Simple State Machine NEW Objectives: Deisgn a simple state machine. In Figure 6.3, what is the purpose for the arrows going from S1 to S0 and from S4 to S3? Why are these needed? What are the advantages of using state variables instead of a series of IF…T..
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ECET 230 Week 7 Homework NEW 1. Is the state machine below a Moore machine or a Mealy machine? Explain your rationale. 3. Using the state diagram in Figure 10.44 on page 663 of the Dueck textbook, briefly explain the operation of the circuit shown. 4.Create the VHDL text file for the state ..
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ECET 230 Week 7 iLab Traffic Light Design Program NEW This lab will take a simple three light, two-way intersection as in figure 1.0 and create a working program for it. Based on the timing chart 2.0, I will create a VHDL file and run a simulation to achieve a basic formula for how the intersecti..
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